K6T1008C2E - CMOS SRAM
K6T1008C2E Family Document Title 128Kx8 bit Low Power CMOS Static RAM Revision History Revision No.
History 0.0 Design target 1.0 Finalize - Improve tWP form 55ns to 50ns for 70ns product.
- Remove 55ns speed bin from industrial product.
1.01 Errata correction 2.0 Revise 3.0 Revise - Add 55ns parts to industrial products.
CMOS SRAM Draft Data October 12, 1998 August 30, 1999 Remark Preliminary Final December 1, 1999 February 14, 2000 March 3, 2000 Final Final The attached datasheets
K6T1008C2E Features
* Process Technology: TFT
* Organization: 128Kx8
* Power Supply Voltage: 4.5~5.5V
* Low Data Retention Voltage: 2V(Min)
* Three state o
