* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled a
KM416S4030C Datasheet (124.27 KB)
KM416S4030C
Samsung semiconductor
124.27 KB
1m x 16bit x 4 banks synchronous dram.
KM416S4030C
Revision History
Revision 1 (May 1998)
- ICC2 N value (10mA) is changed to 12mA.
Preliminary CMOS SDRAM
Revision .2 (June 1998)
- tSH (-.
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