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KM416S4030C 1M x 16Bit x 4 Banks Synchronous DRAM

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Description

KM416S4030C Revision History Revision 1 (May 1998) - ICC2 N value (10mA) is changed to 12mA.Preliminary CMOS SDRAM Revision .2 (June 1998) - tSH (-.
The KM416S4030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high.

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Datasheet Specifications

Part number
KM416S4030C
Manufacturer
Samsung semiconductor
File Size
124.27 KB
Datasheet
KM416S4030C_Samsungsemiconductor.pdf
Description
1M x 16Bit x 4 Banks Synchronous DRAM

Features

* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled a

Applications

* ORDERING INFORMATION Part No. KM416S4030CT-G/F7 KM416S4030CT-G/F8 KM416S4030CT-G/FH KM416S4030CT-G/FL KM416S4030CT-G/F10 Max Freq. 143MHz 125MHz 100MHz 100MHz 100MHz LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE

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