LC8900KQ Datasheet PDF - Sanyo Digital Audio Interface Receiver Specs

LC8900KQ - Digital Audio Interface Receiver

Datasheet Summary

Description

Input data output pin.

However, its output is fixed at the low level if the DIN4 input pin is selected.

RC oscillation pin RC oscillation pin Input pin select pin Input pin select pin High level = LPF time constant select mode.

Features

On-chip PLL circuit: enables the LSI operation to be synchronous to the transmitted EIAJ format input signals.
Four input pins and one output pin: The output pin enables the input data to be sent as they are.
Two data output function modes: 20-bit data LSB first mode and 16-bit data MSB first mode.
Four output clocks: Bit clock, LRCK, 384Fs and 256Fs. All these clocks are synchronized to the data.
Various signal outputs: copy inhibit, emphasis on.

Datasheet Details

Part number	LC8900KQ
Manufacturer	Sanyo
File Size	146.15 KB
Description	Digital Audio Interface Receiver
Datasheet	LC8900KQ Datasheet
Additional preview pages of the LC8900KQ datasheet.

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Full PDF Text Transcription

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Ordering number : EN4128B CMOS LSI LC8900KQ Digital Audio Interface Receiver Preliminary Overview The LC8900KQ is a CMOS LSI circuit chip that can be used to enable the EIAJ CP-1201 formatted data transmission between digital audio equipment. It is used by the receiving end and operates synchronously with input signals. This chip demodulates input signals into normally-formatted signals. Applicational and Functional Concept Features • On-chip PLL circuit: enables the LSI operation to be synchronous to the transmitted EIAJ format input signals. • Four input pins and one output pin: The output pin enables the input data to be sent as they are. • Two data output function modes: 20-bit data LSB first mode and 16-bit data MSB first mode.

Published: Apr 25, 2005 |