TC74AC109P Datasheet - Toshiba

TC74AC109P Dual J-K Flip-Flop

TC74AC109P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC109P, TC74AC109F Dual J-K Flip Flop with Preset and Clear The TC74AC109 is an advanced high speed CMOS DUAL J- K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on positiv.

TC74AC109P Features

* High speed: fmax = 200 MHz (typ.) at VCC = 5 V

* Low power dissipation: ICC = 4 μA (max) at Ta = 25°C

* High noise immunity: VNIH = VNIL = 28% VCC (min)

* Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.

TC74AC109P Datasheet (284.74 KB)