WCSN0436V1P Datasheet (Weida Semiconductor)

WCSN0436V1P, 128Kx36 Pipelined SRAM

The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The WCSN0436V1P is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive R

WCSN0436V1P Features

* Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736

* Supports 166-MHz bus operations with zero wait states

* Data is transferred on every clock

* Internally self-timed output buffer control to eliminate the need to use