WCSS0232V1P Datasheet - Weida Semiconductor

WCSS0232V1P 64K x 32 Synchronous-Pipelined Cache RAM

The WCSS0232V1P is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[15:0] GW BWE BW 3 BW2 BW1 MODE (A[1:0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D D DQ[31:24] Q BYTE.

WCSS0232V1P Features

* Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states

* Fully registered inputs and outputs for pipelined operation

* 64K x 32 common I/O architecture

* Single 3.3V power supply

* Fast clock-to-output times www.DataSheet4U.com All

WCSS0232V1P_WeidaSemiconductor.pdf