WCSS0418V1P Datasheet - Weida Semiconductor

WCSS0418V1P 256K x 18 Synchronous-Pipelined Cache RAM

The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[17:0] GW BWE BW 1 BW0 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D 16 18 18 16 D DQ[1.

WCSS0418V1P Features

* Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states

* Fully registered inputs and outputs for pipelined operation

* 256K by 18 common I/O architecture

* 3.3V core power supply

* 2.5V / 3.3V I/O operation

* Fast clock-to-ou

WCSS0418V1P Datasheet (707.55 KB)