* doze, nap, sleep and dynamic power management. The WED3C755E8M-XBX multichip package consists of: 755 RISC processor (E die revision) Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 Cache Frequency (300MHz/ 150MHz, 350MHz/175MHz) Ma
WED3C755E8M-XBX Datasheet (377.53 KB)
WED3C755E8M-XBX
White Electronic Designs Corporation
377.53 KB
Risc microprocessor multi-chip package.
www.DataSheet4U.com White Electronic Designs WED3C755E8M-XBX RISC MICROPROCESSOR MULTI-CHIP PACKAGE OVERVIEW The WEDC 755E/SSRAM multichip package .
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