* doze, nap, sleep and dynamic power management. The WED3C7558M-XBX multichip package consists of: 755 RISC processor Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 Cache Frequency (300MHz/ 150MHz, 350MHz/175MHz) Maximum 60x Bus freq
WED3C7558M-XBX Datasheet (571.02 KB)
WED3C7558M-XBX
White Electronic Designs
571.02 KB
Risc microprocessor.
www.datasheet4u.com White Electronic Designs WED3C7558M-XBX RISC Microprocessor Multichip Package OVERVIEW The WEDC 755/SSRAM multichip package is .
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