WED3EG7233S-JD3 Features
* Double-data-rate architecture DDR200 and DDR266
* JEDEC design specified Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output,
WED3EG7233S-D3_WhiteElectronicDesigns.pdf
Datasheet Details
WED3EG7233S-JD3, WED3EG7233S-D3
White Electronic Designs
345.83 KB
256mb - 2x16mx72 ddr sdram unbuffered.
This datasheet PDF includes multiple part numbers: WED3EG7233S-JD3, WED3EG7233S-D3.
Please refer to the document for exact specifications by model.
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WED3EG7233S-JD3 Distributor
