A3S56D30GTP

The A3S56D30GTP is 256M Double Data Rate Synchronous DRAM designed by Zentel.

Product Overview

Zentel

Datasheet Details

Part number	A3S56D30GTP
Manufacturer	Zentel
File Size	1.55 MB
Description	256M Double Data Rate Synchronous DRAM
Datasheet	A3S56D30GTP-Zentel.pdf
Additional preview pages of the A3S56D30GTP datasheet.

Product details

Description

A3S56D30GTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40GTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

Features

- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - CAS latency - 2 / 2.5 / 3 (programmable) Burst length - 2 / 4 / 8 (progr.

📁 Similar Datasheet

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Other Datasheets by Zentel

A3S56D30ETP - (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM
A3S56D30FTP - 256M Double Data Rate Synchronous DRAM
A3S56D40ETP - (A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM
A3S56D40FTP - 256M Double Data Rate Synchronous DRAM
A3S56D40GTP - 256M Double Data Rate Synchronous DRAM
A3S28D30FTP - 128M Double Data Rate Synchronous DRAM

Published: Sep 1, 2015 |