A3S56D40GTP Datasheet - Zentel

A3S56D40GTP 256M Double Data Rate Synchronous DRAM

A3S56D30GTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40GTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output dat.

A3S56D40GTP Features

* - VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each pos

A3S56D40GTP Datasheet (1.55 MB)