Part number:
A3S12D30ETP
Manufacturer:
Powerchip
File Size:
2.10 MB
Description:
512mb ddr sdram.
Datasheet Details
A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, A3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe, and output
A3S12D30ETP Features
* - Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5) - Vdd=Vddq=2.6V+0.1V (for speed grade -5) - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transit
Datasheet Details
A3S12D30ETP
Powerchip
2.10 MB
512mb ddr sdram.
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