A3S28D40JTP Datasheet, Dram, Zentel

A3S28D40JTP Features

• Dram - VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clo

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A3S28D40JTP

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Zentel

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📄 Datasheet

Description:

128m double data rate synchronous dram. A3S28D40JTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address s

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A3S28D40JTP

Zentel

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