CD74HCT10 - Triple 3-Input NAND Gates
(Texas Instruments)
CDx4HCT10 Triple 3-Input NAND Gates
CD74HCT10, CD54HCT10
SCHS404 – JUNE 2020
1 Features
• LSTTL input logic patible – VIL(max) = 0.8 V, VIH(min) .
CD74HCT107 - Dual J-K Flip-Flop
(Texas Instruments)
Data sheet acquired from Harris Semiconductor SCHS139D
March 1998 - Revised October 2003
CD54HC107, CD74HC107, CD74HCT107
Dual J-K Flip-Flop with Res.
CD74HCT109 - Dual J-K Flip-Flop
(Texas Instruments)
Data sheet acquired from Harris Semiconductor SCHS140E
March 1998 - Revised October 2003
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
Dual J-K Flip-F.
CD74HCT10E - Triple 3-Input NAND Gates
(Texas Instruments)
CDx4HCT10 Triple 3-Input NAND Gates
CD74HCT10, CD54HCT10
SCHS404 – JUNE 2020
1 Features
• LSTTL input logic patible – VIL(max) = 0.8 V, VIH(min) .
CD74HCT10M - Triple 3-Input NAND Gates
(Texas Instruments)
CDx4HCT10 Triple 3-Input NAND Gates
CD74HCT10, CD54HCT10
SCHS404 – JUNE 2020
1 Features
• LSTTL input logic patible – VIL(max) = 0.8 V, VIH(min) .
CD74HCT112 - Dual J-K Flip-Flop
(Texas Instruments)
Data sheet acquired from Harris Semiconductor SCHS141H
March 1998 - Revised October 2003
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Dual J-K Flip-F.