CD74HCT112 - Dual J-K Flip-Flop
* Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times * Asynchronous Set and Reset * Complementary Outputs * Buffered Inputs * TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, * Fanout (Over Temperature Ran
