CDCLVP110 - Low-Voltage 1:10 LVPECL/HSTL
The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution.
The CDCLVP110 can accept two clock sources into an input multiplexer.
The
CDCLVP110 Features
* 1
* Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
* Fully Compatible With LVECL/LVPECL/HSTL
* Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
* Selectable Clock Input Through CLK_SEL
* Low-Output Skew
