* 1 2:4 Differential Buffer
* Selectable Clock Inputs Through Control Terminal
* Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
* Four LVPECL Outputs
* Maximum Clock Frequency: 2 GHz
* Maximum Core Current Consumption: 45 mA
* Very Low A
CDCLVP1204 Datasheet (1.38 MB)
CDCLVP1204
1.38 MB
High-performance clock buffer.
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CDCLVP1204
SCAS880F
* AUGUST 2009 .
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