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CDCLVP1216 High-Performance Clock Buffer

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Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP1216 SCAS877F * MAY 2009 * REVISED JAN.
The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL.

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Features

* 1 2:16 Differential Buffer
* Selectable Clock Inputs Through Control Pin
* Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
* 16 LVPECL Outputs
* Maximum Clock Frequency: 2 GHz
* Maximum Core Current Consumption: 110 mA
* Very Low Additi

Applications

* Wireless Communications
* Telecommunications/Networking
* Medical Imaging
* Test and Measurement Equipment INP0 INN0 INP1 INN1 Functional Block Diagram VCC VCC VCC VCC VCC VCC IN_MUX LVPECL OUTP[150] 16 OUTN[150] 16 IN_SEL VAC_REF Reference Generator G

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