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CDCLVP1102 High-Performance Clock Buffer

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Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP1102 SCAS884D * AUGUST 2009 * REVISED .
The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS.

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Features

* 1 1:2 Differential Buffer
* Single Clock Input
* Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL
* Two LVPECL Outputs
* Maximum Clock Frequency: 2 GHz
* Maximum Core Current Consumption: 33 mA
* Very Low Additive Jitter:

Applications

* Wireless Communications
* Telecommunications/Networking
* Medical Imaging

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