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CDCLVP1212 High-Performance Clock Buffer

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Description

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP1212 SCAS886E * AUGUST 2009 * REVISED .
The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL.

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Features

* 1 2:12 Differential Buffer
* Selectable Clock Inputs Through Control Terminal
* Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
* 12 LVPECL Outputs
* Maximum Clock Frequency: 2 GHz
* Maximum Core Current Consumption: 88 mA
* Very Low Ad

Applications

* Wireless Communications
* Telecommunications/Networking
* Medical Imaging
* Test and Measurement Equipment INP0 INN0 INP1 INN1 IN_SEL VAC_REF Functional Block Diagram VCC VCC VCC VCC VCC VCC IN_MUX LVPECL OUTP[110] 12 OUTN[110] 12 Reference Generator GN

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