* 1 2:12 Differential Buffer
* Selectable Clock Inputs Through Control Terminal
* Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
* 12 LVPECL Outputs
* Maximum Clock Frequency: 2 GHz
* Maximum Core Current Consumption: 88 mA
* Very Low Ad
CDCLVP1212 Datasheet (1.78 MB)
CDCLVP1212
1.78 MB
High-performance clock buffer.
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CDCLVP1212
SCAS886E
* AUGUST 2009
* REVISED .
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