* 1
* 2 >400 Mbps (200 MHz) Switching Rates
* 50 ps Differential Skew (Typical)
* 2.5 ns Maximum Propagation Delay
* 3.3V Power Supply Design
* Flow-Through Pinout
* Power Down High Impedance on LVDS Inputs
* Low Power Design (18mW @ 3.3V Static)
DS90LV018A Datasheet (774.18 KB)
DS90LV018A
774.18 KB
3v lvds single cmos differential line receiver.
DS90LV018A
www.ti.com
SNLS014D
* JUNE 1998
* REVISED APRIL 2013
DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
Check for.
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