* 1
* 2 Deserializes One to Six Bus LVDS Input Serial Data Streams with Embedded Clocks
* IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Modes
* Parallel Clock Rate 16-66MHz
* On Chip Filtering for PLL
* High Impedance Inputs Upon Power Off (Vcc = 0V)
SCAN926260 Datasheet (841.50 KB)
SCAN926260
841.50 KB
Six 1 to 10 bus lvds deserializers.
SCAN926260
www.ti.com
SNLS153H
* JUNE 2002
* REVISED APRIL 2013
SCAN926260 Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and .
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