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ASM5P2309A - (ASM5P2305A / ASM5P2309A) 3.3V Zero Delay Buffer

Download the ASM5P2309A datasheet PDF. This datasheet also covers the ASM5P2305A variant, as both devices belong to the same (asm5p2305a / asm5p2309a) 3.3v zero delay buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

ASM5P2309A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks.

It accepts one reference input and drives out nine low-skew clocks.

It is available in a 16-pin package.

Key Features

  • 15MHz to 133MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs.
  • Output-output skew less than 250pS. Device-device skew less than 700pS. One input drives 9 outputs, grouped as 4 + 4 + 1(ASM5P2309A). One input drives 5 outputs (ASM5P2305A). Less than 200 pS cycle-to-cycle jitter is compatible with Pentium® based systems. Test Mode to bypass PLL (ASM5P2309A onl.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ASM5P2305A_AllianceSemiconductorCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ASM5P2309A
Manufacturer Alliance Semiconductor Corporation
File Size 429.20 KB
Description (ASM5P2305A / ASM5P2309A) 3.3V Zero Delay Buffer
Datasheet download datasheet ASM5P2309A Datasheet

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Other Datasheets by Alliance Semiconductor Corporation

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A 3.3V Zero Delay Buffer rev 1.6 General Features ƒ ƒ ƒ 15MHz to 133MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 250pS. Device-device skew less than 700pS. One input drives 9 outputs, grouped as 4 + 4 + 1(ASM5P2309A). One input drives 5 outputs (ASM5P2305A). Less than 200 pS cycle-to-cycle jitter is compatible with Pentium® based systems. Test Mode to bypass PLL (ASM5P2309A only, Refer Select Input Decoding Table). Available in 16pin 150-mil SOIC, 4.4 mm TSSOP (ASM5P2309A), and in 8pin 150-mil SOIC package (ASM5P2305A). ƒ 3.3V operation, advanced 0.35µ CMOS technology.