Datasheet Details
| Part number | ASM5CVF857 |
|---|---|
| Manufacturer | Alliance Semiconductor |
| File Size | 266.17 KB |
| Description | 2.5V Wide-Range Frequency Clock Driver |
| Datasheet |
 ASM5CVF857 Datasheet
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General Description
This PLL clock buffer is designed for a VDD of 2.5V, AVDD of 2.5V and differential data input and output ASM5CVF857 is characterized for operation from 0°C to 85°C.
levels.
DDR Memory Modules / Zero Delay Board Fan Out.
Key Features
- as Features.
- www. DataSheet4U. com and when the PDB input is low. When the input frequency increases to greater than approximately 20MHz, the PLL will be turned back on, the inputs and outputs will be enabled, and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC). The PLL in the ASM5CVF857 clock driver uses the input clocks (CLK_INT, CLKINC) and the feedback clocks (FB_INT, FB_INC) to provide high-perfor.