ASM5I9350 Datasheet PDF (3.3V 1:10 LVCMOS PLL Clock Generator) | Download Alliance Semiconductor ASM5I9350

ASM5I9350 - 3.3V 1:10 LVCMOS PLL Clock Generator

Description

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200MHz PLL-based clock driver designed for high speed clock distribution applications.

Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999

www.alsc.

Features

Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation ASM5I9350 The ASM5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2. These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output ca.

Datasheet Details

Part number	ASM5I9350
Manufacturer	Alliance Semiconductor
File Size	510.54 KB
Description	3.3V 1:10 LVCMOS PLL Clock Generator
Datasheet	ASM5I9350 Datasheet
Additional preview pages of the ASM5I9350 datasheet.

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Full PDF Text Transcription

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July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation ASM5I9350 The ASM5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2. These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18.

Published: May 9, 2008 |