ASM5I9350 Datasheet 3.3V 1:10 LVCMOS PLL Clock Generator

Manufacturer: Alliance Semiconductor

ASM5I9350 3.3v 1:10 lvcmos pll clock generator by Alliance Semiconductor - Datasheet Preview

Datasheet Details

Part number	ASM5I9350
Manufacturer	Alliance Semiconductor
File Size	510.54 KB
Description	3.3V 1:10 LVCMOS PLL Clock Generator
Download	ASM5I9350 Download (PDF)

General Description

The ASM5I9350 is a low-voltage high-performance does not apply.

200MHz PLL-based clock driver designed for high speed clock distribution applications.

Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice.

Overview

July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator.

Key Features

Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation ASM5I9350 The ASM5I9350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table 2. These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output ca.

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