ASM5I9351 Datasheet 9-Output Zero Delay Buffer

Manufacturer: Alliance Semiconductor

Datasheet Details

The ASM5I9351 is a low voltage high performance clock directly feeds the output dividers.

This mode is fully static and the minimum input clock frequency specification does not apply.

200MHz PLL-based zero delay buffer designed for high speed clock distribution applications.

July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay.

Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.5V or 3.3V operation ASM5I9351 The ASM5I9351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table.2. These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output can dr.

Part Number	Description
ASM5I9350	3.3V 1:10 LVCMOS PLL Clock Generator
ASM5I9352	11-Output Zero Delay Buffer
ASM5I961C	Low Voltage Zero Delay Buffer
ASM5I961P	Low Voltage Zero Delay Buffer
ASM5I9653A	3.3V 1:8 LVCMOS PLL Clock Generator
ASM5I9658	3.3V 1:10 LVCMOS PLL Clock Generator
ASM5I9772A	12-Output Zero Delay Buffer
ASM5I9773A	12-Output Zero Delay Buffer
ASM5I9774A	12-Output Zero Delay Buffer
ASM5I9775A	14-Output Zero Delay Buffer