ASM5I9352 Datasheet 11-Output Zero Delay Buffer

Manufacturer: Alliance Semiconductor

Datasheet Details

The ASM5I9352 is a low voltage high performance 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications.

When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers.

This mode is fully static and the minimum input clock frequency specification does not apply.

July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay.

Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz ASM5I9352 The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and.

Part Number	Description
ASM5I9350	3.3V 1:10 LVCMOS PLL Clock Generator
ASM5I9351	9-Output Zero Delay Buffer
ASM5I961C	Low Voltage Zero Delay Buffer
ASM5I961P	Low Voltage Zero Delay Buffer
ASM5I9653A	3.3V 1:8 LVCMOS PLL Clock Generator
ASM5I9658	3.3V 1:10 LVCMOS PLL Clock Generator
ASM5I9772A	12-Output Zero Delay Buffer
ASM5I9773A	12-Output Zero Delay Buffer
ASM5I9774A	12-Output Zero Delay Buffer
ASM5I9775A	14-Output Zero Delay Buffer