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ASM5I9352 - 11-Output Zero Delay Buffer

Description

The ASM5I9352 is a low voltage high performance 200MHz PLL-based zero delay buffer designed for high speed clock distribution applications.

When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers.

Features

  • Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz ASM5I9352 The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and.

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Datasheet preview – ASM5I9352

Datasheet Details

Part number ASM5I9352
Manufacturer Alliance Semiconductor
File Size 513.00 KB
Description 11-Output Zero Delay Buffer
Datasheet download datasheet ASM5I9352 Datasheet
Additional preview pages of the ASM5I9352 datasheet.

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Full PDF Text Transcription

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July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Features ƒ ƒ ƒ Output frequency range: 25MHz to 200MHz Output frequency range: 16.67MHz to 200MHz Input frequency range: 16.67MHz to 200MHz ASM5I9352 The ASM5I9352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:22. ƒ 2.
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