ASM5I9653A Datasheet PDF | Alliance Semiconductor

Alliance Semiconductor ASM5I9653A

The ASM5I9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25MHz. The ASM5I9653A has a differential LVPECL reference input long with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer.

Part No.	ASM5I9653A
Datasheet	ASM5I9653A Download
Manufacturer	Alliance Semiconductor
Description	3.3V 1:8 LVCMOS PLL Clock Generator
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FEATURES

1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9653A running at either 4x or 8x of the reference clock frequency. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are to the fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The ASM5I9653A is fully 3.3V compatible and requires no external loop filter components.