ASM5I9653A Overview
The ASM5I9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the ASM5I9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5MHz or 50 to...
ASM5I9653A Key Features
- 1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply
- Generates clock signals up to 125MHz
- PLL guaranteed to lock down to 145MHz, output frequency = 36.25MHz
- Maximum output skew of 150 pS Differential LVPECL reference clock input External PLL feedback Drives up to 16 clock line
- Santa Clara, CA
- Tel: 408.855.4900
- Fax: 408.855.4999
- alsc.co