ASM5I9653A Datasheet PDF (3.3V 1:8 LVCMOS PLL Clock Generator) | Download Alliance Semiconductor ASM5I9653A

ASM5I9653A - 3.3V 1:8 LVCMOS PLL Clock Generator

Description

The ASM5I9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock.

Normal operation of the ASM5I9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback).

Features

1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9653A running at either 4x or 8x of the reference clock frequency. The ASM5I9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25MHz. The ASM5I9653A has a differential LVPECL reference input long with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The devic.

Datasheet Details

Part number	ASM5I9653A
Manufacturer	Alliance Semiconductor
File Size	687.06 KB
Description	3.3V 1:8 LVCMOS PLL Clock Generator
Datasheet	ASM5I9653A Datasheet
Additional preview pages of the ASM5I9653A datasheet.

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Full PDF Text Transcription

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July 2005 rev 0.2 3.3V 1:8 LVCMOS PLL Clock Generator Features 1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9653A running at either 4x or 8x of the reference clock frequency. The ASM5I9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25MHz. The ASM5I9653A has a differential LVPECL reference input long with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis.

Published: May 9, 2008 |