ASM5I9658 Datasheet PDF (3.3V 1:10 LVCMOS PLL Clock Generator) | Download Alliance Semiconductor ASM5I9658

ASM5I9658 - 3.3V 1:10 LVCMOS PLL Clock Generator

Description

The ASM5I9658 is a 3.3V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications.

Features

1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9658 and the reference clock frequency determines the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the ASM5I9658 is running at either 2x or 4x of the reference clock frequency. The ASM5I9658 has a differential LVPECL reference input along with an external feedback input. The ASM5I9658 is ideal for use as a zero delay, low skew fanout bu.

Datasheet Details

Part number	ASM5I9658
Manufacturer	Alliance Semiconductor
File Size	619.13 KB
Description	3.3V 1:10 LVCMOS PLL Clock Generator
Datasheet	ASM5I9658 Datasheet
Additional preview pages of the ASM5I9658 datasheet.

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Full PDF Text Transcription

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July 2005 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator Features 1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply ASM5I9658 and the reference clock frequency determines the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the ASM5I9658 is running at either 2x or 4x of the reference clock frequency. The ASM5I9658 has a differential LVPECL reference input along with an external feedback input. The ASM5I9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis.

Published: May 9, 2008 |