Datasheet4U Logo Datasheet4U.com

ASM5I9773A - 12-Output Zero Delay Buffer

Description

The ASM5I9773A is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high speed clock distribution applications.

Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com Notice:

Features

  • Output frequency range: 8.33MHz to 200MHz Input frequency range: 6.25MHz to 125MHz 2.5V or 3.3V operation ASM5I9773A The ASM5I9773A features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4,.

📥 Download Datasheet

Datasheet preview – ASM5I9773A

Datasheet Details

Part number ASM5I9773A
Manufacturer Alliance Semiconductor
File Size 663.52 KB
Description 12-Output Zero Delay Buffer
Datasheet download datasheet ASM5I9773A Datasheet
Additional preview pages of the ASM5I9773A datasheet.
Other Datasheets by Alliance Semiconductor

Full PDF Text Transcription

Click to expand full text
June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features ƒ ƒ ƒ Output frequency range: 8.33MHz to 200MHz Input frequency range: 6.25MHz to 125MHz 2.5V or 3.3V operation ASM5I9773A The ASM5I9773A features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible output can drive 50Ω series- or parallel-terminated transmission lines.
Published: |