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ASM5I9774A - 12-Output Zero Delay Buffer

Description

The ASM5I9774A is a low-voltage high-performance 125MHz PLL-based zero delay buffer designed for highspeed clock distribution applications.

When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers.

Features

  • Output frequency range: 8.3MHz to 125MHz Input frequency range: 4.2MHz to 62.5MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 2 LVCMOS reference clock inputs 150 pS max output-output skew PLL bypass mode ‘SpreadTrak’ Output enable/disable Pin compatible with MPC9774 and CY29774AI. Industrial temperature range:.
  • 40°C to +85°C 52Pin 1.0mm TQFP package RoHS Compliance ASM.

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Datasheet preview – ASM5I9774A

Datasheet Details

Part number ASM5I9774A
Manufacturer Alliance Semiconductor
File Size 513.59 KB
Description 12-Output Zero Delay Buffer
Datasheet download datasheet ASM5I9774A Datasheet
Additional preview pages of the ASM5I9774A datasheet.

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Full PDF Text Transcription

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June 2005 rev 0.3 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Features ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output frequency range: 8.3MHz to 125MHz Input frequency range: 4.2MHz to 62.5MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 2 LVCMOS reference clock inputs 150 pS max output-output skew PLL bypass mode ‘SpreadTrak’ Output enable/disable Pin compatible with MPC9774 and CY29774AI. Industrial temperature range: –40°C to +85°C 52Pin 1.0mm TQFP package RoHS Compliance ASM5I9774A The ASM5I9774A features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table.
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