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AS4DDR16M72PBG - 16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

Datasheet Summary

Description

BGA Locations SYMBOL F4, F16, G5, G15, K1, K12, CKx, CKx L2, L13, N6, M8 DESCRIPTION Clock: CKx and CKx are differential clock inputs.

All address and control input signals are sampled on the crossing of the positive edge of CKx and negative edge of CKx.

Features

  • DDR SDRAM Data Rate = 200, 250, 266, 333Mbps.
  • Package:.

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Datasheet Details

Part number AS4DDR16M72PBG
Manufacturer Austin Semiconductor
File Size 403.15 KB
Description 16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit
Datasheet download datasheet AS4DDR16M72PBG Datasheet
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Full PDF Text Transcription

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i PEM 1.2 G b SDRAM-DDR Gb Austin Semiconductor, Inc. AS4DDR16M72PBG 16Mx72 DDR SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ DDR SDRAM Data Rate = 200, 250, 266, 333Mbps „ Package: BENEFITS „ 40% SPACE SAVINGS „ Reduced part count „ Reduced I/O count • „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/received with data, i.e.
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