AS4DDR32M16 Overview
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The 512Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation.
AS4DDR32M16 Key Features
- VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
- Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (has two
- one per byte)
- Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
- Differential clock inputs (CK and CK#)
- mands entered on each positive CK edge
- DQS edge-aligned with data for READs; center-aligned with data for WRITEs
- DLL to align DQ and DQS transitions with CK
- Four internal banks for concurrent operation
- Data mask (DM) for masking write data (has two-one per byte)