CY2DM1502 Description
The CY2DM1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 CML, HCSL, or LVPECL to CML fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating.
CY2DM1502 Key Features
- One current mode logic (CML), High-speed current steering logic (HCSL), or low-voltage positive emitter-coupled logic (L
- 20-ps maximum output-to-output skew
- 480-ps maximum propagation delay
- 0.15-ps maximum additive RMS phase jitter at 156.25 MHz
- Up to 1.5 GHz operation
- 8-pin thin shrunk small outline package (TSSOP) package
- 2.5-V or 3.3-V operating voltage [1]
- mercial and industrial operating temperature range