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CY7C1009B - 128K x 8 Static RAM

General Description

The CY7C109B / CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits.

Key Features

  • High speed.
  • tAA = 12 ns.
  • Low active power.
  • 495 mW (max. 12 ns).
  • Low CMOS standby power.
  • 55 mW (max. ) 4 mW.
  • 2.0V Data Retention.
  • Automatic power-down when deselected.
  • TTL-compatible inputs and outputs.
  • Easy memory expansion with CE1, CE2, and OE options put Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip En.

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📁 Similar Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1009 Straight 1-Row BergStik II Headers
CY7C1009D 1-Mbit (128 K x 8) Static RAM
CY7C1009V33 Straight 1-Row BergStik II Headers
CY7C1006B 256K x 4 Static RAM
CY7C1007 (CY7C107 / CY7C1007) 1M x 1 Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
009B CY7C109B CY7C1009B 128K x 8 Static RAM Features • High speed — tAA = 12 ns • Low active power — 495 mW (max. 12 ns) • Low CMOS standby power — 55 mW (max.) 4 mW • 2.0V Data Retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options put Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH.