CY7C1386KV33 Datasheet | Cypress

CY7C1386KV33 CY7C1387KV33 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM Features - Supports bus operation up to 200 MHz - Available speed grades are 200, and 167 MHz - Registered inputs and outputs for pipelined operation - Optimal for performance (double-cycle deselect) - Depth expansion without wait state - 3.3 V core power supply (VDD) - 2.5 V or 3.3 V I/O power supply (VDDQ) - Fast clock-to-output times - 3 ns (for 200 MHz device) - Provides high performance 3-1-1-1 access rate - User selectable burst counter supporting interleaved or linear burst sequences - Separate processor and controller address strobes - Synchronous self-timed writes - Asynchronous output enable - CY7C1386KV33 available in JEDEC-standard Pb-free 100-pin TQFP. CY7C1387KV33 available in JEDEC-standard Pb-free 100-pin TQFP - ZZ sleep mode option Functional Description The CY7C1386KV33/CY7C1387KV33 SRAM integrates...