| Part number | CY7C1418BV18 |
|---|---|
| Datasheet | CY7C1418BV18_CypressSemiconductor.pdf |
| File Size | 731.55 KB |
| Manufacturer | Cypress (now Infineon) |
| Description | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
|
|
The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K.
See all Cypress (now Infineon) datasheets
| Part Number | Description |
|---|---|
| CY7C1418AV18 | (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418JV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418KV18 | 36-Mbit DDR II SRAM Two-Word Burst Architecture |
| CY7C141 | 1K x 8 Dual-Port Static RAM |
| CY7C1410AV18 | (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture |
| CY7C1410JV18 | (CY7C14xxJV18) SRAM 2-Word Burst Architecture |
| CY7C1410V18 | (CY7C14xxV18) SRAM 2-Word Burst Architecture |
| CY7C1411AV18 | (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture |
| CY7C1411BV18 | (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture |
| CY7C1411JV18 | (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture |
