Full PDF Text Transcription for CY7C1418BV18 (Reference)
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CY7C1418BV18. For precise diagrams, and layout, please refer to the original PDF.
Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided.
CY7C1418BV18 Datasheet
