Datasheet4U Logo Datasheet4U.com

CY7C1418KV18 - 36-Mbit DDR II SRAM Two-Word Burst Architecture

General Description

The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Key Features

  • 36-Mbit density (2M × 18, 1M × 36).
  • 333 MHz clock for high bandwidth.
  • Two-word burst for reducing address bus frequency.
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems.
  • Synchronous in.

📥 Download Datasheet

Full PDF Text Transcription for CY7C1418KV18 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for CY7C1418KV18. For precise diagrams, and layout, please refer to the original PDF.

CY7C1418KV18/CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture 36-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 36-Mbit density (2M × 18, 1M × 36) ■ ...

View more extracted text
rd Burst Architecture Features ■ 36-Mbit density (2M × 18, 1M × 36) ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Synchronous internally self-timed writes ■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH ■ Operates similar to DDR-I device

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1418AV18 (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C141 1K x 8 Dual-Port Static RAM
CY7C1410AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C1411AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18 (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18 (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture