CY7C1471BV25 Description
CY7C1471BV25 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/1 M × 72) Flow-Through SRAM with NoBL™.
CY7C1471BV25 Key Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Supports up to 133 MHz bus operations with zero wait states
- Data transfers on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self timed output buffer control to eliminate the need
- Registered inputs for flow through operation
- Byte Write capability
- 2.5-V I/O supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)