CY7C1471V25 - (CY7C147xV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
Datasheet Summary
Description
The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.
Features
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
Can support up to 133-MHz bus operations with zero wait states.
Data is transferred on every clock.
Pin compatible and functionally equivalent to ZBT™ devices.
Internally self-timed output buffer control to eliminate the need to use OE.
CY7C1470BV25- (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1470BV33- 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
CY7C1470V25- 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1470V33- (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
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PRELIMINARY
CY7C1471V25 CY7C1473V25 CY7C1475V25
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V/1.8V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 8.
CY7C1471V25 Datasheet
