CY7C1470BV25- (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1470BV33- 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
CY7C1470V25- 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1470V33- (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
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CY7C1471BV33 CY7C1473BV33
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■ No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states ■ Data is transferred on every clock ■ Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self timed output buffer control to eliminate the need
to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O supply (VDDQ) ■ Fast clock-to-output times
❐ 6.
CY7C1471BV33 Datasheet
