Datasheet Details
| Part number | CY7C1381D |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 1.29 MB |
| Description | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| Datasheet | CY7C1381D-Cypress.pdf |
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Overview: Not Remended for New Designs. CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (512K × 36/1M × 18) Flow-Through.
| Part number | CY7C1381D |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 1.29 MB |
| Description | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| Datasheet | CY7C1381D-Cypress.pdf |
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The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz version).
A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
| CY7C1381KV33 | 18-Mbit Flow-Through SRAM | Cypress Semiconductor | |
| CY7C1381KVE33 | 18-Mbit Flow-Through SRAM | Cypress Semiconductor |
| Part Number | Description |
|---|---|
| CY7C1380S | 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM |
| CY7C1382S | 18-Mbit (512 K x 36/1 M x 18) Pipelined SRAM |
| CY7C1383D | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383F | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1386S | 18-Mbit (512 K x 36) Pipelined DCD Sync SRAM |
| CY7C131AE | 1K/2K x 8 Dual-Port Static RAM |
| CY7C131E | 1K/2K x 8 Dual-Port Static RAM |
| CY7C136AE | 1K/2K x 8 Dual-Port Static RAM |
| CY7C136E | 1K/2K x 8 Dual-Port Static RAM |
| CY7C1370C | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |