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CY7C1381D - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Datasheet Summary

Description

The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133 MHz version).

Features

  • Supports 133 MHz bus operations.
  • 512K × 36 and 1M × 18 common I/O.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O supply (VDDQ).
  • Fast clock-to-output time.
  • 6.5 ns (133 MHz version).
  • Provides high performance 2-1-1-1 access rate.
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • CY7C.

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Datasheet Details

Part number CY7C1381D
Manufacturer Cypress
File Size 1.29 MB
Description 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Datasheet download datasheet CY7C1381D Datasheet
Additional preview pages of the CY7C1381D datasheet.

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Full PDF Text Transcription

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Not Recommended for New Designs. CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM Features ■ Supports 133 MHz bus operations ■ 512K × 36 and 1M × 18 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output time ❐ 6.5 ns (133 MHz version) ■ Provides high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self-timed write ■ Asynchronous output enable ■ CY7C1381D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP.
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