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CY7C1381D Datasheet 18-mbit (512k X 36/1m X 18) Flow-through Sram

Manufacturer: Cypress (now Infineon)

Overview: Not Remended for New Designs. CY7C1381D CY7C1383D CY7C1383F 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM 18-Mbit (512K × 36/1M × 18) Flow-Through.

General Description

The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512K × 36 and 1M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133 MHz version).

A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Key Features

  • Supports 133 MHz bus operations.
  • 512K × 36 and 1M × 18 common I/O.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O supply (VDDQ).
  • Fast clock-to-output time.
  • 6.5 ns (133 MHz version).
  • Provides high performance 2-1-1-1 access rate.
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • CY7C.

CY7C1381D Distributor