CY7C1381D Overview
Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).
CY7C1381D Key Features
- Supports 133 MHz bus operations
- 512K × 36 and 1M × 18 mon I/O
- 3.3 V core power supply (VDD)
- 2.5 V or 3.3 V I/O supply (VDDQ)
- Fast clock-to-output time
- 6.5 ns (133 MHz version)
- Provides high performance 2-1-1-1 access rate
- User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed write
