EDJ1108DBSE - 128M words x 8 bits 1G bits DDR3 SDRAM

Datasheet Summary

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

Elpida Memory

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Datasheet Details

Part number	EDJ1108DBSE
Manufacturer	Elpida Memory
File Size	2.19 MB
Description	128M words x 8 bits 1G bits DDR3 SDRAM
Datasheet	EDJ1108DBSE Datasheet
Additional preview pages of the EDJ1108DBSE datasheet.

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Full PDF Text Transcription

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DATA SHEET 1G bits DDR3 SDRAM EDJ1108DBSE (128M words × 8 bits) EDJ1116DBSE (64M words × 16 bits) Specifications • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (EDJ1108DBSE)  8M words × 16 bits × 8 banks (EDJ1116DBSE) • Package  78-ball FBGA (EDJ1108DBSE)  96-ball FBGA (EDJ1116DBSE)  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V • Data rate  1600Mbps/1333Mbps (max.

Published: Apr 13, 2015 |