EDJ2108DEBG - 2G bits DDR3 SDRAM

Elpida Memory

Key Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

EDJ2108DEBG 2g bits ddr3 sdram by Elpida Memory - Datasheet Preview

Datasheet Details

Part number	EDJ2108DEBG
Manufacturer	Elpida Memory
File Size	297.00 KB
Description	2G bits DDR3 SDRAM
Datasheet	EDJ2108DEBG Datasheet

More Datasheets from Elpida Memory

Part Number	Description
EDJ2116DEBG	2G bits DDR3 SDRAM
EDJ1108DBSE	128M words x 8 bits 1G bits DDR3 SDRAM
EDJ1108DJBG	1G bits DDR3 SDRAM
EDJ1116DBSE	64M words x 16 bits 1G bits DDR3 SDRAM
EDJ1116DJBG	1G bits DDR3 SDRAM
EDJ4204EFBG	1024M words x 4 bits 4G bits DDR3L SDRAM
EDJ4208EFBG	512M words x 8 bits 4G bits DDR3L SDRAM
EDJ4216EFBG	256M words x 16 bits 4G bits DDR3L SDRAM

Full PDF Text Transcription for EDJ2108DEBG (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for EDJ2108DEBG. For precise diagrams, tables, and layout, please refer to the original PDF.

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COVER DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG (256M words × 8 bits) EDJ2116DEBG (128M words × 16 bits) Specifications • Density: 2G bits • Organization — 32M words × 8 bits × 8 banks (EDJ2108DEBG) — 16M words × 16 bits × 8 banks (EDJ2116DEBG) • Package — 78-ball FBGA (EDJ2108DEBG) — 96-ball FBGA (EDJ2116DEBG) — Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.