EDJ2108DEBG Datasheet | Elpida Memory

Features - Double-data-rate architecture: two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; centeraligned with data for WRITEs - Differential clock inputs (CK and /CK) - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Data mask (DM) for write data - Posted /CAS by programmable additive latency for better mand and data bus efficiency - On-Die Termination (ODT) for better signal quality - Synchronous ODT - Dynamic ODT - Asynchronous ODT - Multi Purpose Register (MPR) for pre-defined pattern read out - ZQ calibration for DQ drive and ODT - /RESET pin for Power-up sequence and reset function - SRT range: - Normal/extended - Programmable Output driver impedance control - Seamless BL4 access with bank-grouping - Applied only for DDR3-1333 and 1600 Document. No. E1712E60 (Ver. 6.0) Date Published October 2013 (K) Japan Printed in Japan URL: http://.elpida. ©Elpida Memory, Inc. 2010-2013 EDJ2108DEBG, EDJ2116DEBG Ordering Information Part number EDJ2108DEBG-MU-F EDJ2108DEBG-JS-F EDJ2108DEBG-GN-F EDJ2108DEBG-DJ-F EDJ2116DEBG-MU-F EDJ2116DEBG-JS-F EDJ2116DEBG-GN-F EDJ2116DEBG-DJ-F Die revision Organization (words × bits) Internal banks JEDEC speed bin (CL-t RCD-t RP) DDR3-2133 (14-14-14) DDR3-1866 (13-13-13) DDR3-1600 (11-11-11) DDR3-1333 (9-9-9) DDR3-2133 (14-14-14) DDR3-1866 (13-13-13) DDR3-1600 (11-11-11) DDR3-1333 (9-9-9) Package 78-ball...