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EDJ2116DEBG - 2G bits DDR3 SDRAM

Download the EDJ2116DEBG datasheet PDF. This datasheet also covers the EDJ2108DEBG variant, as both devices belong to the same 2g bits ddr3 sdram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Double-data-rate architecture: two data transfers per clock cycle.
  • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
  • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
  • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
  • Differential clock inputs (CK and /CK).
  • DLL aligns DQ and DQS transitions with CK transi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EDJ2108DEBG-ElpidaMemory.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EDJ2116DEBG
Manufacturer Elpida Memory
File Size 297.00 KB
Description 2G bits DDR3 SDRAM
Datasheet download datasheet EDJ2116DEBG Datasheet

Full PDF Text Transcription for EDJ2116DEBG (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for EDJ2116DEBG. For precise diagrams, tables, and layout, please refer to the original PDF.

View original datasheet text
COVER DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG (256M words × 8 bits) EDJ2116DEBG (128M words × 16 bits) Specifications • Density: 2G bits • Organization — 32M words × 8 bits × 8 banks (EDJ2108DEBG) — 16M words × 16 bits × 8 banks (EDJ2116DEBG) • Package — 78-ball FBGA (EDJ2108DEBG) — 96-ball FBGA (EDJ2116DEBG) — Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.