EDJ2116DEBG Overview
COVER DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG (256M words × 8 bits) EDJ2116DEBG (128M words × 16 bits) Specifications Density: VDD, VDDQ = 1.5V ± 0.075V Data rate 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max) Spread Spectrum Clock (SSC) Sweep rate: down spread 1% (20kHz to 60kHz) 1KB page size (EDJ2108DEBG) Row address:.
EDJ2116DEBG Key Features
- Double-data-rate architecture: two data transfers per clock cycle
- The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
- Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the recei
- DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge; data and data mask referenced to both edges of DQS
- Data mask (DM) for write data
- Posted /CAS by programmable additive latency for better mand and data bus efficiency
- On-Die Termination (ODT) for better signal quality