EDJ4204EFBG - 1024M words x 4 bits 4G bits DDR3L SDRAM

Datasheet Summary

Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

Elpida Memory

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Datasheet Details

Part number	EDJ4204EFBG
Manufacturer	Elpida Memory
File Size	392.78 KB
Description	1024M words x 4 bits 4G bits DDR3L SDRAM
Datasheet	EDJ4204EFBG Datasheet
Additional preview pages of the EDJ4204EFBG datasheet.

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Full PDF Text Transcription

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COVER PRELIMINARY DATA SHEET 4G bits DDR3L SDRAM EDJ4204EFBG (1024M words × 4 bits) EDJ4208EFBG (512M words × 8 bits) EDJ4216EFBG (256M words × 16 bits) Specifications • Density: 4G bits • Organization — 128M words × 4 bits × 8 banks (EDJ4204EFBG) — 64M words × 8 bits × 8 banks (EDJ4208EFBG) — 32M words × 16 bits × 8 banks (EDJ4216EFBG) • Package — 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG) — 96-ball FBGA (EDJ4216EFBG) — Lead-free (RoHS compliant) and Halogen-free • Power supply: 1.35V (typ) — VDD = 1.283V to 1.45V — Backward compatible for VDD, VDDQ = 1.5V ± 0.

Published: Jul 14, 2015 |