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EMP38K03HPC Datasheet Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor

Manufacturer: Excelliance MOS

Datasheet Details

Part number EMP38K03HPC
Manufacturer Excelliance MOS
File Size 551.46 KB
Description Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet download datasheet EMP38K03HPC Datasheet

General Description

: Q1 Q2 BVDSS 30V 30V RDSON (MAX.)@VGS=10V RDSON (MAX.)@VGS=4.5V ID @TC=25℃ 7.0mΩ 9.4mΩ 41A 4.0mΩ 5.4mΩ 60A ID @TA=25℃ 16A 21A Dual N Channel MOSFET UIS, Rg 100% Tested RoHS & Halogen Free & TSCA Compliant ▪ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL LIMITS Q1 Q2 UNIT Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current1 Avalanche Current Avalanche Energy Repetitive Avalanche Energy2 TC = 25 °C TC = 100 °C TA = 25 °C TA = 70 °C L = 0.1mH L = 0.05mH VGS ±20 ±20 V ID 41 60 26 38 ID 16 21 A 12 17 IDM 68 102 IAS 34 53 EAS 57.8 140.45 mJ EAR 28.9 70.225 Power Dissipation Power Dissipation TC = 25 °C TC = 100 °C TA = 25 °C TA = 70 °C PD 20.8 25 8.3 10 W PD 3.1 3.1 W 2 2 Operating Junction & Storage Temperature Range Tj, Tstg -55 to 150 °C ▪100% UIS testing in condition of VD=25V, L=0.1mH, VG=10V, IL=21A,RG=25Ω, Rated VDS=30V N-CH_Q1 ▪100% UIS testing in condition of VD=25V, L=0.1mH, VG=10V, IL=32A,RG=25Ω, Rated VDS=30V N-CH_Q2 ▪THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM Q1 Q2 UNIT Junction-to-Case RθJC 6 5 Junction-to-Ambient3 t≦10s RθJA Steady-State RθJA 40 40 °C/W 65 65 1Pulse width limited by maximum junction temperature.

2Duty cycle < 1% 3The value of RθJA is measured with the device mounted on 1in2 FR-4 board with 2oz.

Copper, in a still air environment with TA =25°C.

Overview

EMP38K03HPC Dual N-Channel Logic Level Enhancement Mode Field Effect Transistor ▪Product Summary: ▪.