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GTLP8T306 - 8-Bit LVTTL/GTLP Bus Transceiver

Description

The GTLP8T306 is an 8-bit bus transceiver that provides LVTTL to GTLP signal level translation.

The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels.

Features

  • s Bidirectional interface between GTL/GTLP and LVTTL logic levels s Output Edge Rate Control to minimize noise on the GTLP port s Power up/down/off high impedance for live insertion s Standard 245 function s CMOS technology for low power dissipation s 5V tolerant inputs and outputs on the A-Port s Bus-hold data inputs on the A-Port eliminates the need for external pull-up resistors on unused inputs s LVTTL compatible driver and control inputs s Flow through pinout optimizes PCB layout s Open dra.

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Full PDF Text Transcription

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GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver September 1997 Revised April 2000 GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver General Description The GTLP8T306 is an 8-bit bus transceiver that provides LVTTL to GTLP signal level translation. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal output edge-rate control and is process, voltage, and temperature (PVT) compensated.
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