FPD1000V Datasheet | Filtronic

FEATURES (1.8 GHz) - 31 d Bm Linear Output Power - 16 d B Power Gain - Useable Gain to 10 GHz - 41 d Bm Output IP3 - Maximum Stable Gain of 20 d B - 50% Power-Added Efficiency - 10V Operation / Plated Source Thru-Vias DRAIN BOND PAD (2X) 1W POWER PHEMT GATE BOND PAD (2X) - DESCRIPTION AND APPLICATIONS DIE SIZE (µm): 650 x 800 DIE THICKNESS: 75µm BONDING PADS (µm): >70 x 65 The FPD1000V is a discrete depletion mode Al Ga As/In Ga As pseudomorphic High Electron Mobility Transistor (p HEMT), optimized for power applications in L- and C-Bands. The FPD1000V includes Source plated thru-vias, and does not require wire bonds to the Source. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers. - ELECTRICAL SPECIFICATIONS AT 22°C Parameter Power at 1d B Gain pression Power Gain at d B Gain pression Maximum Stable Gain S21/S12 Power-Added Efficiency at 1d B Gain pression 3 -Order Intermodulation Distortion ΓS and ΓL tuned for Optimum IP3 Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| ΘCC rd Symbol P1d B G1d B MSG PAE IM3 Test Conditions VDS = 10V; IDS = 200 m A ΓS and ΓL tuned for Optimum IP3 VDS = 10V; IDS = 200 m A ΓS and ΓL tuned for Optimum IP3 VDS = 10 V; IDS = 200m A PIN = 0d Bm, 50Ω system VDS = 10V; IDS = 200 m A ΓS and ΓL tuned for Optimum IP3 VDS = 10V; IDS = 200 m A POUT = 19 d Bm (single-tone level) VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS ≅ +1 V VDS = 1.3 V; VGS = 0 V VGS = -3 V VDS = 1.3 V; IDS = 2.4 m A IGS = 2.4 m A IGD = 2.4 m A See Note on following page Min 30 14.5 Typ 31 16.0 20 50 Max Units d Bm RF SPECIFICATIONS MEASURED AT f = 1.85 GHz USING CW SIGNAL d B % -46 480 650 1100 720 20 0.7 6 20 0.9 8 22 22 -44 720 d Bc m A m A m S 50 1.4 µA V V V °C/W Phone:...